Circuit-based, zero-allocation frontend skeleton enabling deterministic, nanosecond-tier, lock-free data pipelines via flat, preallocated arrays, compiler-enforced memory budgets, SoA ECS and native UI bindings.
Mathematical Runtime Certification via Structural Static Analysis for Kotlin Multiplatform.
Autumn aims to be an aerospace-grade, high-frequency execution framework that introduces Clock-Aware Programming to commodity CPUs. By treating memory as a pure static topology and enforcing mathematical cycle limits at the compiler level, Autumn's goal is to allow standard CI/CD pipelines to cryptographically certify software execution bounds.
Autumn v1.2.0 natively scales the L1-cache bounds into Kubernetes-native Zero-Copy Mmap Multicasting across perfectly strict unidirectional boundaries:
Traditional managed software hides temporal uncertainty behind dynamic thread schedulers, expensive atomic locks, and unpredictable Garbage Collection. Hardware, however, is deterministic because physical timing is a fundamental design rule.
Autumn attempts to bring this physical rigor to Kotlin by exploring three architectural pillars:
Because memory layouts are entirely flattened and allocated statically at boot (AutumnMemoryBank), there is no pointer-chasing and no Garbage Collector footprint. Applications map directly to the CPU's L1/L2 cache, opening the door for high-performance zero-copy auditing and deterministic state databases.
Every piece of application state lives inside a statically allocated Autumn Memory Bank. There are no blocking connections to read files, sockets, or standard input streams. I/O is resolved via Kernel Bypass (AF_XDP/eBPF) for local networks, or POSIX fread for offline testing.
By attaching directly to XDP rings via native C-interop, the pipeline translates 4 million real historical NASDAQ_ITCH50 packets per second deterministically on a single commodity hardware core.
Modern software manages slow communication (Network, Disk, Databases, HTTP) using abstractions like Coroutines, Promises, or Async/Await. These mechanisms introduce massive overhead through context switching and heap-allocated state machines.
Autumn discards the asynchronous model entirely by abstracting all costly communication into a BoundaryChannel. The Business Logic is modeled as a pure Finite State Machine (FSM) that never blocks, never sleeps, and never waits. It aims to execute deterministically, computing state transitions instantly. Any interaction with the unpredictable "outside world" is pushed across a zero-copy ring-buffer boundary. Whether the event is an AF_XDP network packet, an io_uring SSD read, or an HTTP payload, the application purely reacts to memory-mapped state transitions. Hardware latency is conceptually partitioned away from the logic.
Autumn explores eliminating atomic variables and Mutex locks in the hot path. Data entering the system is passed through a lock-free HashRouter, which shards the data and statically routes it to a specific Arbiter core. Because the execution budget is bounded and thread affinity is isolated, the goal is for synchronization to happen by timing schedule, rather than runtime blocking.
autumn-certifier)Because the architecture depends on deterministic memory and pinned routines, Autumn aims to physically prove its behavior.
During compilation, the K2 TopologySynthesisTransformer extracts the exact Control Flow Graphs (CFG) and loop boundaries (@MaxIterations) into a JSON topology. The autumn-certifier Gradle plugin then executes this exact trace natively on Linux via perf stat, validating that the physical hardware trace does not exceed the mathematical ceilings generated by the compiler.
Because Autumn treats data structures purely as isolated index math on memory, the Business Logic does not care how the bytes arrive. We formalized three transport tiers (ADR-0030) ensuring zero-allocation network ingestion across all cloud and bare-metal environments:
flowchart LR
subgraph Cloud Tier
A[java.nio DatagramChannel] -.->|JVM / Android| E
end
subgraph Bare-Metal Tier
B[POSIX sys/socket.h] -.->|Microseconds| E
C[AF_XDP Kernel Bypass] -.->|Nanoseconds| E
end
subgraph Offline Tier
D[POSIX fread PCAP] -.->|Batch Profiling| E
end
E["@UdpGateway / @XdpGateway"] -->|Zero-Copy| F[("AutumnMemoryBank")]
F -->|Lock-Free Ring| G["@HotPath Execution Engine"]
style F fill:#003472,stroke:#000,stroke-width:2px,color:#fff
style G fill:#E34F26,stroke:#000,stroke-width:2px,color:#fff
java.nio sockets map elegantly to managed Kubernetes workloads, Android, and macOS.linuxX64 architectural builds leverage native LLVM POSIX recvfrom and AF_XDP hooks to unlock 700k+ to 34M+ ops/sec throughput strictly to the NIC.Once bytes organically cross the boundary layer into the AutumnMemoryBank, the remaining pipeline operates flawlessly:
n### Kotlin K2 Compiler Integration (A Hardware Description Language for the JVM/Native)
Autumn effectively acts as a hardware description language that compiles natively to the JVM and LLVM. The Autumn compiler plugin intercepts the Kotlin Abstract Syntax Tree (AST) to generate and resolve data layouts that standard Kotlin runtimes cannot mathematically support. By simply placing declarative annotations (@BoundaryChannel, @Pipelined), developers write what looks like standard Kotlin business logic.
flowchart TD
A["Idiomatic Kotlin Code<br/>@CycleBudget / @Observe"] --> B("K2 Compiler IR/FIR Hook")
subgraph Compiler Phase
B --> C["AST TopologySynthesisTransformer"]
B --> D["CycleBudgetVisitor Math Limits"]
end
C --> E("LLVM linuxX64 Native Binaries")
C --> F("JVM C2 JIT Bytecode")
C --> G(("topology.json Telemetry"))
D --> G
G -.-> H["Autumn IDE Performance Center<br/>Compose UI / Gutter Icons"]
style E fill:#003472,stroke:#000,stroke-width:2px,color:#fff
style H fill:#E34F26,stroke:#000,stroke-width:2px,color:#fff
Autumn effectively acts as a hardware description language that compiles natively to the JVM. The Autumn compiler plugin intercepts the Kotlin Abstract Syntax Tree (AST) to generate and resolve data layouts that standard Kotlin runtimes cannot mathematically support. By simply placing declarative annotations (@BoundaryChannel, @Pipelined), developers write what looks like standard Kotlin business logic. Under the hood, Autumn synthesizes architecture allowing literal OS-bypass for ultra-low latency execution:
Because Autumn scales from bare-metal servers to consumer mobile phones, the architecture falls into two distinct execution topologies:
This topology uses the structural annotations (@BoundaryChannel, @ColdChannel) to generate a lock-free, multi-core mechanical sympathy pipeline capable of tens of millions of operations per second.
+-----------------------+
| NIC / AF_XDP / Socket |
+-----------+-----------+
| @BoundaryChannel (Wait-free Ring Buffer FSM Device)
v
+-----------------------+
| Autumn HashRouter | <-- Shards workload sequentially by Session/Symbol
+-----------+-----------+
|
| SPSC Lock-Free Queue
v
+-----------------------+
| Autumn Arbiter (FSM) | <-- Core-Affinity Pinned Business Logic
+-----+-----------+-----+
| |
| | @ColdChannel (Zero-copy multicasting fan-out)
| v
| +-----------------------+
| | Risk / Logging Server |
| +-----------------------+
|
| @RegisterChannel (Primitive Offset Routing)
v
+-----------------------+
| OrderBook / Matching | <-- Direct AutumnMemoryBank (SoA) Mutation
+-----------------------+
This topology treats the UI as an external physical display attached to an embedded system. It completely decouples network processing from Android/iOS frame drops by converting standard object graphs into pure integer arrays.
+-----------------------+
| Network Sockets (Raw) |
+-----------+-----------+
| @BoundaryChannel (FSM Device)
v
+-----------------------+ +-----------------------+
| Autumn Config Parser | ----> | String / Byte Registry|
| (Zero-Allocation) | | (Flat Native Offsets) |
+-----------+-----------+ +-----------------------+
|
v
+-----------------------+
| Epoch State Engine | <-- Coalesces logical state ticks
+-----------+-----------+
|
v
+-----------------------+
| Native UI / Compose | <-- Wakes up and resolves raw offsets straight to pixels
+-----------------------+
docs/adr/
autumn-core/ # Compiler pacts and limits
autumn-compiler-plugin/ # K2 AST visitor enforcing allocations
autumn-gradle-plugin/ # Gradle hooks for plugin injection
autumn-resolver/ # In-place Network Handoff API
autumn-config/ # Zero-alloc JSON parsing and registries
autumn-buckets/ # Content offset mappers
autumn-state/ # Circuit-based Epoch observer
autumn-ui/ # SoC Motherboard and Native UI Compose Binder
autumn-benchmarks/ # JMH latency profiling and zero-allocation hardware proofs
Getting started guidance will be added as the project skeleton evolves. For now, this repository establishes the architectural decisions and module boundaries for the framework.
Architectural decisions live in docs/adr/ and capture the initial shape of Autumn:
Autumn's goal is to bridge the gap between high-level application development and Hardware Description Languages (HDL). Toward this effort, future development focuses heavily on moving telemetry out of the console and directly into the developer's IDE:
Because the autumn-compiler-plugin performs massive amounts of A Priori static analysis (calculating L1 cache bounds, physical memory padding, and cycle costs), we plan to export this exact mathematical layout via a standard telemetry contract (e.g., autumn-topology.json).
A companion IntelliJ plugin will map this data back onto the source code, creating a real-time Hardware Schematic inside the editor:
@ColdChannel & @IpcGateway)The memory architecture in Autumn is already perfectly flat. Bypassing Inter-Process Communication (IPC) bottlenecks entirely, future development will allow mapping multiple distinct Autumn applications directly onto the same disk-backed or /dev/shm shared memory block.
Using .mmap() natively, the Hot Path (e.g. Market Data parsing running on isolated cores 4-15) writes lock-free indices directly to memory via explicitly unidirectional @ColdChannel fire-and-forget handoffs. Downstream Cold Path applications (Risk, DB Logging, Websockets on shared cores 0-3) map the same memory block as their ingress and read sequentially.
This physically eliminates and bidirectional circular dependencies! A slow database write on Core 0 can never lock or stall the Hot Strategy execution on Core 4. You achieve the sub-microsecond determinism of a monolith, but the restartability/crash-tolerance of distributed microservices.
autumn-observatory)Standard APM agents and profilers destroy latency by allocating objects and issuing locking system calls. Future integration will allow developers to annotate any handler with @Observe("MetricName").
The Autumn compiler will automatically weave hardware clock instructions (NativeClock.rdtsc()) around the function and fire-and-forget the raw execution cycles into a background @ColdChannel. This allows a separate thread (or processor) to calculate exact production P99s completely out-of-band without disturbing the sub-microsecond hot path.
Autumn turns idiomatic Kotlin into locked-down DPDK-tier pipelines. You define the shape of the data and the channel, and the K2 compiler synthesizes the execution polling loops and pointer math statically.
Autumn bypasses standard object allocation by replacing DTO flows with an emulated hardware interrupt wire. Here is how you bind Autumn to a Compose UI:
Because Autumn handles the payloads purely natively as bytes, making the network request does not fill the garbage collector. The OS socket bytes sit in StringRegistry, the EpochStateEngine evaluates the exact slot mutations, and Compose only executes a String allocation inside resolveTextPrimitive when drawing the physical pixel!
Autumn is strictly modular. You only pay for what you pull. The Autumn K2 Compiler Gradle plugin must be applied to the project, and then you select the runtime dependencies based on your physical target constraint.
For zero-copy network ingestion, native parsing, and hardware telemetry.
plugins {
id("io.github.alchevrier.autumn.compiler") version "1.2.0"
}
dependencies {
implementation("io.github.alchevrier:autumn-core:1.2.0")
implementation("io.github.alchevrier:autumn-resolver:1.2.0") // Sockets & Network bounds
implementation("io.github.alchevrier:autumn-observatory:1.2.0") // Zero-allocation telemetry
}
For 120fps stutter-free Jetpack Compose / SwiftUI applications driven by purely static arrays.
plugins {
id("io.github.alchevrier.autumn.compiler") version "1.2.0"
}
dependencies {
implementation("io.github.alchevrier:autumn-core:1.2.0")
implementation("io.github.alchevrier:autumn-state:1.2.0") // EpochStateEngine / Reactivity
implementation("io.github.alchevrier:autumn-ui:1.2.0") // Canvas / Pixel bindings
}
For heavy flat-mapped SoA (Structure of Arrays) state, configs, and raw binary string pooling.
plugins {
id("io.github.alchevrier.autumn.compiler") version "1.2.0"
}
dependencies {
implementation("io.github.alchevrier:autumn-core:1.2.0")
implementation("io.github.alchevrier:autumn-config:1.2.0") // JSON / schema registry without GC
implementation("io.github.alchevrier:autumn-buckets:1.2.0") // Zero-copy String representations
}
When building products on top of Autumn, you transition from Event-Driven Asynchronous Programming to Holistic Time-Triggered Circuit Design. This represents a fundamental shift in programming paradigms, even when compared to ultra-low-level C/C++/Rust:
In traditional low-latency codebases (even in advanced Rust or DPDK architectures), systems are built from disjointed parts:
epoll wakes up a thread.The developer is constantly managing temporal uncertainty. Code is full of if (lock.tryAcquire()), Arc<Mutex<T>>, or atomic compares. The system architecture is fragmented across hardware, OS, and application tiers.
With Autumn, you are designing a single, unified "System on a Chip" (SoC) in software.
You declare your topologies statically:
@BoundaryChannel(capacity = 16777216, sharded = 4)
val inboundNetwork = AutumnChannel<OrderEvent>()
From that single declaration, the compiler has a holistic view of your entire application's lifetime from boot to exit:
By collapsing the Networking Boundary, Memory Allocator, Thread Scheduler, and Compilation AST into a single unified theory, you aren't writing software; you are utilizing LLVM to natively synthesize hardware logic circuits onto commodity CPUs.
@BoundaryChannel) and pinned tightly to L1 hardware schedulers. Egress is explicitly Cold (@ColdChannel), physically segregating external network backpressure away from the pure computation loop dynamically without thread-locking loops.@ColdChannel decorated with an @IpcGateway natively intercepts memory property getters/setters during AST evaluations in the K2 Compiler Plugin. Applications natively bind values to explicit C-interop /dev/shm POSIX pointers dynamically. This achieves flawless multi-process execution via identical Kubernetes emptyDirs mapped deterministically to structural integer bounds without a single allocation or TCP loop.linuxX64), Autumn easily achieves a median cross-thread pipeline latency of ~37 nanoseconds, with a completely flat <120 ns P99.99. No Garbage Collection, no OS thread locks, just pure instruction-level parallelism.@CycleBudget, the compiler mathematically guarantees a locked frame rate across Android, iOS, and WebAssembly, absolutely impervious to GC stutters.IntArray state engine, ensuring the FSM natively coalesces pulses and never chokes on backpressure.@InjectBudget.@ThreadCacheBudget validation: Physically analyzes stack sizes and inline "value class" footprints to mathematically reject compilation if a hot loop (like a market ticks loop) exceeds physical L1 cache hardware limits.@Pipelined): Converts idiomatic Kotlin interfaces into Flyweight Data-Oriented structures. During Pass 1, Autumn detects all requested channel capacities across the codebase, merges matching struct capacities, and statically generates a single contiguous wait-free SoA array initialized directly in main().@RegisterChannel, @BoundaryChannel, @ColdChannel): Rather than generating expensive pointer loops to route channels, the plugin natively injects the resolved array bounds directly into the respective lock-free SPSCRingBuffer.globalIndexOffset initialization bytecode.@Speculative): Controls burst routing execution at compile time, seamlessly applying predictable loop-bounds (e.g., burstWindow = 400) to minimize hardware clock queries. This natively supports WebAssembly execution constraints and provides direct theoretical control over thermal CPU levels at compile time.@Contended, achieving DPDK-level cross-thread pipeline handoffs at ~29 nanoseconds (34 Million ops/sec) out of the box without special runtime flags or OS-level thread pinning.@BoundaryChannel), polling tightly in the L1 cache. Egress is treated as Cold (@ColdChannel), ensuring fire-and-forget I/O pipelines that physically segregate external network/disk backpressure away from computational hot-paths.mmap() boundaries, applications can map Kubernetes emptyDir /dev/shm mounts perfectly identical to internal value class inline SoA layouts. This allows completely passive, infinite-scale framework topologies seamlessly propagating hardware telemetry across boundaries entirely without GC or TCP/UDP networking loops.autumn-core — core interfaces, shared domain models, and compiler pacts (@LongLived, @InjectBudget).autumn-compiler-plugin — K2 compiler plugin enforcing strictly bounded allocations at build time.autumn-gradle-plugin — Gradle hook required to execute the compiler plugin across platforms.autumn-state — hardware-sympathetic reactivity engine (EpochStateEngine) replacing traditional Flow observers.autumn-buckets — bucket abstractions mapping configuration pointers to raw image/document strings.autumn-resolver — deterministic network boundary (AutumnNetworkEngine) executing in-place handoffs.autumn-config — zero-allocation payload string registry and hardware matrix limit calculator (JsonConfigParser).autumn-ui — native rendering bridge linking platform Canvas text exactly to byte indices.autumn-ide-plugin — JetBrains Compose IntelliJ plugin visualizing cycle limits and structural topology dynamically in the IDE.autumn-benchmarks — bare-metal algorithmic latency analysis proving sub-microsecond throughput (e.g. ITCH 5.0 Order Books).autumn-observatory — zero-allocation telemetry tracking hardware ticks seamlessly via compiler-injected cold channels.@BoundaryChannel and open a node-based visualizer showing the exact flow of data through your FSM ticks, bypassing typical standard "Find Usages" clutter.[24 bytes | 3% L1 Cache] CodeLens hints sitting directly above your @Pipelined structs.tick() handler and see exactly how many ALU CPU cycles the compiler mathematically predicts the frame will cost.@ThreadCacheBudget capacity boundary before you run the gradle build.@BoundaryChannel// 1. Define a Flyweight struct
// This generates no objects; 'index' simply maps into the globally allocated AutumnMemoryBank.
value class OrderEvent(val index: Int) {
// Properties are written idiomatically.
// The K2 compiler plugin statically intercepts these getters and rewrites them into
// pre-computed AutumnMemoryBank offset equations at compile time.
val ref: Long get() = 0L
val price: Int get() = 0
}
// 2. Declare a hardware-sympathetic SPSC ring buffer
// Mathematically padded against false-sharing L1 CPU cache lines
val inboundNetwork = AutumnChannel<OrderEvent>(16777216)
// 3. Define the Hot Loop
// The @LongLived handler is intercepted by K2, unrolling it into a static frame
// tracking the thread-local indices without GC boundaries or OS context switching.
fun onInboundNetwork(idx: Int) {
val event = OrderEvent(idx) // Zero allocation
// Direct primitive array routing (OrderBook SoA logic)
val baseOffset = event.price * MAX_ORDERS
levelOrderRefs[baseOffset + depth] = event.ref
}
// 4. Synthesize the Topology
fun tickServer() {
// The Compiler natively injects a deterministic hardware evaluation frame here,
// pulling bytes directly off the NIC and routing across L1-padded rings.
}
// 1. The Output Binder
// This adapts Autumn's memory matrices to platform-specific graphics.
class MyScreenBinder(
stateEngine: EpochStateEngine,
stringRegistry: StringRegistry
) : AutumnCircuitBinder(stateEngine, stringRegistry) {
// Expose specific coordinates statically configured by @InjectBudget
fun getHeroTitle() = resolveTextPrimitive(coordinateId = 0)
fun getActionLabel() = resolveTextPrimitive(coordinateId = 1)
}
// 2. The Native UI
fun AutumnScreen(binder: MyScreenBinder) {
// A single state trigger. When the global hardware wire pulses,
// this increments, causing Compose to redraw the screen.
var epochTick by remember { mutableStateOf(0) }
LaunchedEffect(binder) {
// Suspend the UI completely until the batch finishes
binder.attachToInterruptWire(this) {
epochTick++ // Emulates an interrupt wakeup
}
}
// Rely on the tick to trigger recomposition,
// then read strictly from the hardware-sympathetic registry
Column {
Text(text = binder.getHeroTitle())
Button(onClick = { /* Fire NetworkHandoff in-place */ }) {
Text(text = binder.getActionLabel())
}
}
}
while(true) loops or epoll handlers. You write onInboundNetwork(event), and the HardwareOscillator acts as an independent clock routing execution ticks at exactly the speed the hardware cache can support.Surfaced from shared tags and platforms — no rankings paid for.