Circuit-based, zero-allocation frontend skeleton enabling deterministic, nanosecond-tier, lock-free data pipelines via flat, preallocated arrays, compiler-enforced memory budgets, SoA ECS and native UI bindings.
Experimental Runtime Execution and Synthesis Framework for Kotlin Multiplatform.
Autumn is an experimental framework attempting to introduce Clock-Aware Programming concepts to commodity software. By enforcing strict memory boundaries and performing static analysis at the compiler level, Autumn explores whether deterministic execution profiles typically reserved for hardware descriptions (like FPGAs) can be emulated within standard software languages.
Autumn is currently a research project. Many features are experimental or planned representations of future architecture, used to guide the development of the compiler plugin.
Traditional software relies on dynamic thread schedulers, OS semaphores, and unpredictable memory allocations. Hardware, however, relies on strict structural schedules. Autumn attempts to model these structural rules within Kotlin:
new Keywords (Zero-Allocation): Objects must declare their spatial layout boundaries at compile-time (e.g. using arrays of flattened types). Dynamic malloc (or GC churn) is forbidden in critical paths.By defining constraints upfront, tools like LLVM (and subsequently hardware synthesizers) have the necessary bounding information to collapse software routines into highly optimal pipelines.
Application code declares bounded structures, channels, gateways, and handlers. The compiler owns physical realization: SoA lowering, region placement, topology export, and the current GPOS boundary-binding bridge.
flowchart LR
SRC["Kotlin declarations<br/>@Pipelined · @BoundaryChannel<br/>@HttpGateway · @BoundaryHandler"]
IR["Autumn K2 compiler<br/>validation + SoA lowering"]
MAP["Physical layout synthesis<br/>absolute offsets + alignment"]
MAN["topology.json v3<br/>banks · regions · schemas<br/>channels · FSM symbols"]
INIT["Generated initialization<br/>provision(totalBytes)"]
RT["Autumn runtime<br/>oscillators + boundary drivers"]
HW["JVM / Native / JS / Wasm<br/>future RTL synthesis"]
SRC --> IR --> MAP
MAP --> MAN
MAP --> INIT
MAN --> RT
INIT --> RT --> HW
The current generated binding is a transitional GPOS implementation. In the ADR-0040 target, the compiler emits gateway descriptors and handler symbols only; AutumnOrchestrator creates and binds platform drivers from the manifest.
All declared memory is compile-time static. Regions are separated by ownership and purpose, not by a static-versus-dynamic lifetime distinction. This prevents structured state and boundary planes from overlapping or writing into each other's memory areas.
flowchart TB
BANK["global memory bank<br/>compiler-calculated total capacity"]
SOA["STRUCTURED_STATE<br/>@Pipelined SoA fields"]
GAP["Unassigned alignment gap"]
HI["BOUNDARY_INGRESS<br/>HTTP request slots"]
HE["BOUNDARY_EGRESS<br/>HTTP response slots"]
OI["BOUNDARY_INGRESS<br/>Ollama response slots"]
OE["BOUNDARY_EGRESS<br/>Ollama request slots"]
BANK --> SOA
BANK --> GAP
BANK --> HI
BANK --> HE
BANK --> OI
BANK --> OE
Topology format v3 records each region's bank, absolute byte offset, capacity, and purpose, plus compiler-owned schema field offsets and fixed slot strides. Boundary drivers receive their fixed offsets from generated code and do not call AutumnMemoryBank.claim(). Runtime claims are rejected after compiler provisioning. Alignment provides spatial separation; target-specific cache residency and cache-set placement remain a separate compiler-analysis milestone.
Bounded @Schema data classes are compiler input for topology v3 physical layouts. HTTP handlers declare HttpRequest<Task> and read request.body.estimate or an allocation-free request.utf8(Task::title) view. The compiler infers strict JSON decode, accepted versions, migration, dedicated body memory, deterministic field-key dispatch, and constant-offset property access from that signature. Standard fixed-binary handlers declare ; the compiler provisions ingress memory, validates exact-width records in place, and lowers the same property syntax. opts into a 24-byte envelope carrying schema family, version, and payload width so declared historical layouts can migrate into a dedicated body plane. Raw exact-width framing remains the default. remains the low-level runtime ABI rather than the normal handler API.
Projects using the Autumn Gradle plugin may commit autumn.schemas.lock.json beside their build file. The compiler validates current declarations against that immutable history and generates fallback descriptors from the lock, so accepted historical Kotlin classes can be removed. Compilation emits build/reports/autumn/schema-history.candidate.json; promote newly declared versions explicitly with ./gradlew autumnLockSchemas. Reusing a locked (schema id, version) with a different layout is a compile error.
On one local JVM microbenchmark, generated JSON-to-slot decoding for a four-field schema measured , close to the linear lookup baseline. For twelve reverse-ordered integer fields, generated dispatch measured versus , a improvement. On that identical wide input, Kotlin serialization measured and , while Jackson measured and about ; generated Autumn measured . The raw typed fixed-binary handler measured ; current-version envelope validation plus handling measured ; and v1 envelope migration plus v2 handling measured , all at . These are development measurements, not portable latency guarantees.
Externally owned binary protocols use the generic @DiscriminatedBinaryMessage and @BinaryField compiler projection rather than pretending to be Autumn schemas. Discriminator position and byte order are declaration-level facts; typed access lowers to constant-offset big- or little-endian reads. ITCH Add Order is the first production-shaped consumer, including its 48-bit timestamp and fixed space-padded ASCII. One local preloaded-memory run measured exact discriminator/length validation plus eight typed reads at 26.44 ns/op and 0 B/op; transport and session framing were outside that measurement.
A separate sustained benchmark compiles and executes the ergonomic handler path: raw request framing and metadata, schema-version selection, strict decode, defaults or declared v1-to-v2 fallback, and typed property access. On the same host with a 64 MiB heap, Autumn current-v2 requests measured , p50 , p99.9 , , and no GC during the 10-second measurement. Kotlin serialization measured , p50 , p99.9 , , and 375 collections. Autumn is therefore not always the fastest median parser; its demonstrated advantage is controller-level ergonomics with bounded final-state publication and no request-driven heap pressure. These are development measurements, not portable latency guarantees. See the for the full current and fallback tables, reproducible commands, guarantee boundary, and fairness limitations.
Autumn is being designed to support two distinct target environments:
This topology attempts to execute network polling algorithms directly on bounded CPU arrays to reduce traditional OS overhead.
+-----------------------+
| NIC / AF_XDP / Socket |
+-----------+-----------+
| (Zero-copy payload extraction)
+-------v-------+
| Ingress Rings | ~ L1 Cache Boundaries
+-------+-------+
|
+------------v-------------+
| Clock-Aware Kotlin Code |
| (No Locks, No Alloc) |
+------------+-------------+
|
+-------v-------+
| Egress Rings | -> Dispatch back to network
+---------------+
The current experimental plugin demonstrates translating Kotlin blocks via AST parsing directly into HLS outputs (like hls::stream semantics) capable of bridging to physical FPGAs.
autumn-core — Channels, boundary drivers, platform memory banks, schedulers, schema serialization, and core annotations.Note: Models such as autumn-resolver, autumn-observatory, and telemetry tracing are partially mocked implementations used to guide the development API contract.
You can test the compiler plugin and generated structures using the provided shootout and synthesis examples:
# Evaluate zero-allocation execution paths locally against Ktor & Spring:
./gradlew :autumn-shootout:run --args="autumn"
./gradlew :autumn-shootout:run --args="ktor"
# Generate the HLS/SystemVerilog translation maps of the Feed Handler:
./gradlew clean :autumn-hls-demo:build
cat autumn-hls-demo/build/reports/autumn/rtl/autumn_synthesized_circuit.sv
Autumn utilizes Architectural Decision Records (ADRs) to track theoretical shifts in framework design. All structural pivots and major synthesis hypotheses are documented within the /docs/adr folder.
The framework is built aggressively on documented architectural theories. While not all are currently implemented natively, they serve as the theoretical underpinning for this research:
@Schema declaration now drives its topology v3 layout, strict JSON projection, exact-width fixed-binary projection, defaults, validation, and typed slot access. Generated JSON key dispatch uses a deterministic byte automaton instead of declaration-order scanning.autumn.schemas.lock.json preserves immutable wire history. Compilation emits a canonical candidate for explicit promotion, while declared historical versions can migrate through an opt-in versioned binary envelope into a dedicated compiler-owned body region.HttpRequest<T> and BinaryMessage<T> handler signatures synthesize validation, accepted-version selection, migration, memory provisioning, and constant-offset property access. Current bindings target GPOS drivers while manifest-owned orchestration remains the architectural target.@DiscriminatedBinaryMessage and @BinaryField declarations project existing wire ABIs into allocation-free BinaryWireView<T> handlers without repacking them as Autumn schemas. Discriminator position, byte order, fixed ASCII, and non-standard integer widths are compile-time facts; NASDAQ ITCH Add Order is the first production-shaped consumer.@[MaxIterations]) to ensure the analysis engine can guarantee worst-case execution time (WCET) bounds.BinaryMessage<Task>@StandardGateway(framing = StandardGatewayFraming.VERSIONED)SchemaSlots416.92 ns/op467.12 ns/op806.88 ns/op2299.67 ns/op2.85x528.75 ns/op896 B/op1090.55 ns/op4064 B/op0 B/op70.21 ns/op122.17 ns/op326.79 ns/op0 B/opHttpRequest<CreateTaskV2>993K ops/s966 ns2.163 us0 B/op1.71M ops/s529 ns2.161 us856 B/opautumn-compiler-plugin — K2 validation, SoA lowering, fixed memory-region synthesis, generated initialization, and topology export.autumn-manifest — Serializable topology v3 contracts for banks, named memory regions, schema layouts, channels, and FSM nodes.autumn-hls-demo — Demonstrates experimental translation of an ITCH Feed Handler to C++ HLS/SystemVerilog.autumn-benchmarks — Local throughput and latency analysis of simple logic models.autumn-demo — A reference implementation outlining usage patterns for future pipelines.Surfaced from shared tags and platforms — no rankings paid for.